Samsung Tech Conference 2006 paper
We present a solution to the critical issues emerged with introduction of 6F2 and 4F2 for 80nm node devices and beyond;especially in periodic island patterns such as DRAM active. The most challenging issue with DRAM active pattern is that the pitch is different for wide and narrow axis. Another issue is the inclination of the pattern by 23 degree in order to attain maximum degree of integration. As a result, the process margin in the wider pitch, we modify the mask layout so that the pitch in wide and narrow direction is almost same. For the case that the ratio between two different pitched is 4:1, we first segmented the pattern into four pieces and then linked them as one. By optimizing both log slope in the narrow and wide pitch simultaneously. Futhermore, the MEEF of the wider pitch has been reduced considerably from 11 to 6. This approach has been applied sucessfully to the 80nm device and will be extended to 60 and even to 50nm devices.
Keyword : 6F2, 4F2, 80nm node, DOF, NILS, MEEF, DRILL
The acceleration of the shinkage in the design rule propelled by the high degree of intergration, increased chip performance and the improvement of the productivity, promoted the introduction of shorter wave length light, as well as various resolution techniques(RET's) known up to date. Nevertheless, difficulties in patterning are more challenging than ever. For a specific case of the Dynamic Random Access Memory(DRAM) active pattern, a general trend to use efficiently the space is the rearrangement and modification of the layout. By adopting 6F2 cell design instead of conventional 8F2, we can obtain a reduction in the cell area by 20%. However, the efficient use of the space means more compact layout which is translated into increased technological obstacle to pattern properly. One of the technological difficultied in patterning is the actual pitch reduction from 160nm to 138nm for 8F2 to 6F2 respectively, as shown in the Fig. 1.
As a result, we ecperience an effective design rule reduction. Another issue raised regarding transition form 8F2 to 6F2 is the inclination of the island cell by 23 degree, where mask fabrication process becomes more complicated. Furthermore, these patterns are not appropriate to pattern with conventional high numerical aperture(NA) illumination since we can not meet with all the process margins. For a 2-dimensional(2-D) pattern having different pitches in two different directions we should consider the modification of the illumination thich can cover big pitch gap between each directions.
In this papter, we propose a new litho-friendly design methodology where both the wide and narrow pitch patterns are printed with increased process margins. We also performed a review on the illumination and found otu an optimized illumination source configurations. The conceptual ideas were confirmed by simulation as well as printed images on the wafer.
2. The analysis of current issues and layout optimization
2.1 Condition of simulation
We start with a review fo the active layout of the 6F2 and 8F2 for 80nm devices, the simulation results and actual images on the wafer. Then we proceed with an analysis of differences between simulation and actual images, and estimated the difficulties in the fabrication process. Finally we propose an optimum method to enhance the process margins of the 6F2 cell design/
First, the simulation was performed with the TOPO(in-house-tool) simulator where the diffusion length was set to 20nm for Gaussian convolution model and vector model considering light refraction in the PR/
The figure2 shows the simulation sequence begining with orifinal mask layout followed by estimation of the corner rounding that occurs during the mask fabrication and finally we analyzed the aerial image taking into account the diffusion of the acid in the resist.
2.2 Simulation resluts comparison of the 6F2 and 8F2
We have summarized in the table 1 the lithographic parameters related with the process of the 6F2 and 8F2, referring to the dimensional characteristics shown in the figure3/
As can be seen in the table 1, the cell pitches of the gate poly(g/P) and bit line(B/L) are 168 and 160nm respectively for the 8F2, the wide and narrow pitched of theactive layer are 672 and 160nm, repectively. The narrow ptich is actually comparable to the minimum feature size of the 80nm device and Mask Error Enahancement Factor(MEEF) values for the narrow and wide axis are 4.9 and 2.9 respectively, which is in an acceptable level for mass production.
On the other hand, the active pattern of the 6F2 cell design is inclined about 23 degree, with respect to the horizontal axis. Therefore, the pitches withrespect G/P and B/L are 176/224nm repectively, but the pitched for the active layer are 570 and 138nm. If we consider the value for the narrow pitch it actually corressponds to the 69nm device, making wores the situation for fabrication process.
The target space critical dimensions(CDs) along the narrow and wide axis are 66 and 84nm respectivelym which are quite smaller than 8F2 cell design. The space Cd is very important in the sense that the storage poly(S-poly) node contact, or buried contact(BC) should ovelap with self-alinged contact(BC SAC) so that the contact resistance is within specification. Therefore, we try to enlarge the bar CD resulting in smaller space CD. As a result, process marings like NILS, EL and DOF worsen for wide axis as can be seen in the table 1. Expecially the NILS is as small as 0.71, which is smaller than the minimum value of 1.0. Also the MEED for the wide and narrow axis increases from 4.7/2.9nm to 10.5/6.5nm, impeding the adoption of the 6F2 cell design for fabrication, since the mask fabrication is pretty difficult/
Now we turn our attention to the exposed wafer image results. As can be seen int the Fig4, the process margin for the 8F2 is much larger than that of the 6F2. The small process marign is mainly originated from the bridging by defocus in the wide axis
2.3 The optimization of the illumination system and mask for 6F2 active margin improvement
In order to determine the optimum illumination system. we first extract the mask spectrum by using a commercial simulator, as shown in the Fig. 5. After analyzing the mask spectrum hexpole was suggested as the best one
To optimize the inner and outer sigma value and the open angle for the pole, we evaluated the NILS, EL, and MEEF for the target CD shown in the FIg. 3.b. To print with high fidelity the narrow pitch, we should consider using high sigma. For a λ of 193nm, the narrow pitch(138nm) might be printed well with NA value of 0.85, which is a commonly used for 80nm device fabrication. As the pitch of the pattern becomes smaller, incident beam which is a commonly used for 80nm device gabrication. As the pitch fo the pattern becomes smaler, incident beam angles for 0th and 1st order increase. In order to docus them, we should also increase the numerical aperture(NA) of the lens tiwh the sifma of the illumination system.
We confront with problems when the patterns that we are going to print are composed of various pitches. Since the illumination system is optimized for printing patterns with narrow pitche, the process margin for the wider pitches defrade. To alleciate this situation, we might consider the design of and illumination system capable to adjust sigma value of the pole. But in reality we do not have such a system at the moment. Otherwise, we adjust the inner sigma value in order to cover patterns with different pitches. For 80nm device 6F2 active layout it is desiable to print narrow patterns, therefore it is inevitable to use narrow sigma. As a result, process margin for the wide pitch becomes tight.
From now on, we propose a mask optimization process taking into account the illumination system. The active layer being considered has a ratio of ablout 4:1, for the narrow and wide axis(Fig.6,a) Since the illumination is optimized for narrow pitch, we adjust the mask layout so that the wide pitch also resembles to the narrow one(Fig.6,b) Therefore, the key point is to divide or segment the pattern and change the mask layout to have same pitch over the entire wafer. We can apply this characteristic to any 2-D periodic patterns regardless of the design rule. The segmentation is carried out along the pattern having longer dimension taking as reference the shorter pitch.
We also propose a variation of the mask oprimization process mentioned preciously, where the segmented pieces are merged as one. We named this mask layout as " Drill acrive" and carried out the process margin evaluation through simulation.(Fig7)
The illumination system optimization was also performed at the same time. We can see in the figure 8, the simulation results of the active layer for current design(a), 4 segment active(b), and Drill tip active(c), We obtained improver process parameter value for the segmented active like NILS and EL, but unexpectedly the MEEF has increased from 10.53 to13. Prior to apply this layout for the production we should investigate first the relation between MEED and the process margin.
It is not sufficient that we understand the reason of MEEF improvement only with equation(1)
Some papers mentioned relation among MEEF, contrast and NILS. Generally, higher NILS and contrast reduce MEEF. But, higher NILS valie of segment layout than current layout doesn't reflect poor MEEF. Therefore, we must keep in mind importance of MEEF as well as NILS and contrast.
On the other hand, all of the process parameters are enhanced for the Drill tip active. The MEEF for the wide and narrow axis decreased to 7.5 and 5.45 respectively. We expect futher enhancement in the MEEF if we increase the NA.
2.4 Mask fabrication and wafer evaluation results
We fabricated attenuated phase shifting mask(att. PSM) for the segmented and Drill tip active, which afree pretty well with the simulation(Fig9). We should perform more complicated cerification on the madk CD, defect control, and then the repair of the mask if necessary
Although the mask pattern was pretty complex, we obtained a clear patterning result as was predicted by the simulation. The figure 11 shows SEM images obtained for the Drill active for defocus value ranging from -0.04 to 0.08. We could obtain a DOF of 0.12, which is a relatively large value for an NA value of 0.92. Futhermore, the MEEF for the wide axis was 5.9(2.0 for narrow axis).
While we analyzed the patterning results we encountered with a suprising result. As shown in the Fig 12 and 13, the shot CD uniformity in the wide axis was improved pretty much. We obtained a value less than 8.6nm, which was 17nm(3sigma) for the previous conventional layout. But we could not see a significant improvement for narrow axis margin.
Since the key point of the Drill active relies on the segmentation of layout, it would be detrimental for CD distribution along the bar. We can avoid the generation of the CD distribution by further optimizing time the mask design.
To ensure the proper operation of device it is strongly demanded that the overlapping region of the active layer with the gate should have minimum CD variation. It it also required that the bar CD should be large enough to meet the dynamic refresh characteristics. In order to address these issues, we arrange the mask layout so that the overlapping area with the gate lied outside of the sequeezed(or negatively biased), as shown in the Fig 14. Therefore, the final version of layout covers many issues regarding the device performance, and as well as the process margin. The enhanced process margin resluts suggest that the Drill active can be applied sucessfully for 6F2 cell design. We are also optimistic about the further application of this concept for 4.5F2 cell desing as well
We estimated the difficulties in the fabrication process by comparing the 6F2 cell design with the 8F2, currently in production. The high value for the MEEF of the current layout obtained from the simulation revealed the difficulties for the mask fabriction. Furthermore, we verified narrow process margins of the current layout through the simulation and printed wafer images. We propose litho-friendly Drill active layout as a solution to the issues mentioned above and verified the improvent of the process parameters by the simulation and printed wafer images as well.
We expect that Drill concept could be extended to all kings of 2D periodic pattern inclusive of DRAM active. Further mask layout and process optimization considering photo margin and reflecting requrement of device characteristics will be continued to 50nm node devices, and more, the rigorous optic principle of DILL will be investigated to extract more accurate rules of layout design as well.
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